Field of Invention
The present invention relates to a chip package and a method of manufacturing a chip package.
Description of Related Art
Electronic products require multiple functions, while the dimension has to remain compact. The chip of the electronic products has ever reducing chip size, and the circuit density increases. The manufacturing of chip package is therefore more challenging. Wafer level chip package is one type of chip packaging. It refers to a production process when all the packaging process and testing are done to the entire wafer, and then it is cut into single chip package.
Chip package very often includes integrated active elements and passive element to allow the chip package to work properly. However, to integrate active elements and passive element requires several patterning and material deposition process. These procedures cost high and take long time, and a shrinking chip dimension leads the manufacturing process even more complex and difficult. Therefore, there is an urgent call for a simplified and fast chip packaging technique.